Renesas Electronics /R7FA6M4AF /SPI0 /SPCMD1

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Interpret as SPCMD1

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CPHA 0 (0)CPOL 0 (00)BRDV 0 (Others)SSLA0 (0)SSLKP 0 (Others)SPB0 (0)LSBF 0 (0)SPNDEN 0 (0)SLNDEN 0 (0)SCKDEN

BRDV=00, SSLA=Others, SCKDEN=0, CPOL=0, CPHA=0, SPNDEN=0, SLNDEN=0, SPB=Others, SSLKP=0, LSBF=0

Description

SPI Command Register 1

Fields

CPHA

RSPCK Phase Setting

0 (0): Select data sampling on leading edge, data change on trailing edge

1 (1): Select data change on leading edge, data sampling on trailing edge

CPOL

RSPCK Polarity Setting

0 (0): Set RSPCK low during idle

1 (1): Set RSPCK high during idle

BRDV

Bit Rate Division Setting

0 (00): Base bit rate

1 (01): Base bit rate divided by 2

2 (10): Base bit rate divided by 4

3 (11): Base bit rate divided by 8

SSLA

SSL Signal Assertion Setting

0 (000): SSL0

0 (Others): Setting prohibited

1 (001): SSL1

2 (010): SSL2

3 (011): SSL3

SSLKP

SSL Signal Level Keeping

0 (0): Negate all SSL signals on completion of transfer

1 (1): Keep SSL signal level from the end of transfer until the beginning of the next access

SPB

SPI Data Length Setting

0 (0x0): 20 bits

0 (Others): 8 bits

1 (0x1): 24 bits

2 (0x2): 32 bits

3 (0x3): 32 bits

8 (0x8): 9 bits

9 (0x9): 10 bits

10 (0xA): 11 bits

11 (0xB): 12 bits

12 (0xC): 13 bits

13 (0xD): 14 bits

14 (0xE): 15 bits

15 (0xF): 16 bits

LSBF

SPI LSB First

0 (0): MSB-first

1 (1): LSB-first

SPNDEN

SPI Next-Access Delay Enable

0 (0): Select next-access delay of 1 RSPCK + 2 PCLKA

1 (1): Select next-access delay equal to the setting in the SPI Next-Access Delay Register (SPND)

SLNDEN

SSL Negation Delay Setting Enable

0 (0): Select SSL negation delay of 1 RSPCK

1 (1): Select SSL negation delay equal to the setting in the SPI Slave Select Negation Delay Register (SSLND)

SCKDEN

RSPCK Delay Setting Enable

0 (0): Select RSPCK delay of 1 RSPCK

1 (1): Select RSPCK delay equal to the setting in the SPI Clock Delay Register (SPCKD)

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